Generic systolic array for genetic algorithms

Implementing a Generic Systolic Array for Genetic Algorithms

Algorithms I. M. Bland Algorithm Engineering Research Group Dept. of Computer Science University of Reading Reading, UK. RG6 6AY [email protected] G. M. Megson Algorithm Engineering Research Group Dept. of Computer Science University of Reading Reading, UK. RG6 6AY [email protected] Abstract|We have designed a highly parallel design for a simple genetic algorithm using a pipeline o...

Systolic Array Library for Hardware Genetic Algorithms

Genetic Algorithms (GAs) are commonly used search algorithms and there is an incentive in accelerate their execution speed using hardware. We present a collection of systolic array designs which perform the Selection, Crossover and Mutation operations of the GA. Although the premise there is considerable generality in the genetic operators is true, it is accepted that GAs often use di erent tec...

Mapping a Generic Systolic Array for Genetic Algorithms onto FPGAs - Theory and Practice

A hardware device for the acceleration of Genetic Algorithms (GAs) is presented. The design computes in O(N + G) time steps using O(N 2) cells. The design is generic in the sense that it performs only the genetic operators and its area is independent of the length of the chromosomes being used. The problems of implementing systolic arrays onto FPGA are discussed and it is concluded that ne-grai...

A systolic array for pyramidal algorithms

Generic Systolic Array for Run-Time Scalable Cores

This paper presents a scalable core architecture based on a generic systolic array. The size of this kind of cores can be adapted in real-time to cover changing application requirements or to the available area in a reconfigurable device. In this paper, the process of scaling the core is performed by the replication of a single processing element using run-time partial reconfiguration. Furtherm...